Power amplifiers are the circuit blocks in wireless transceivers that require the largest power budget because of their relatively low efficiencies. RF designers cannot depend solely on the development better semiconductor devices in advanced deeply scaled process technologies to obtain improved power amplifier performance. The development of new and better circuits, architectures and design methodologies to maximally exploit the available semiconductor devices is very important as well. This thesis investigates a number of techniques that can be used to improve the efficiency of power amplifiers and break the power-frequency tradeoff in power amplifier design. The first technique emphasizes the use of a class E tuned output network as an efficiency enhancement tool for power amplifiers regardless of their bias conditions. A Class E tuned CMOS power amplifier (PA) operating in the 60 GHz band was designed. Design, layout, and parasitic modeling considerations to attain high-efficiency millimeter-wave PA operation are discussed. Both single-ended and differential versions of the single-stage PA were implemented in a 32 nm SOI CMOS process. Peak power added efficiency of 27% (30%), power gain of 8.8 dB (10 dB), and saturated output power > 9 dBm (12.5 dBm) were measured at 60 GHz from the single-ended (differential) PA with 0.9 V supply. The second technique investigated the efficacy of resistance compression networks in an energy recycling network operating at multi-gigahertz frequencies. The resistance compression network reduces the variation in resonant rectifier input impedance seen at the isolation port of an isolating power combiner. The system was operated at 2.14 GHz and was built around Schottky barrier diodes custom fabricated in a 0.13 [mu]m CMOS process. It is the first experimental demonstration that resistance compression networks can be used for energy recycling in multi-gigahertz applications.
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