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MEMORY CELL WITH CHARGE TRAP TRANSISTORS AND METHOD THEREOF CAPABLE OF STORING DATA BY TRAPPING OR DETRAPPING CHARGES
MEMORY CELL WITH CHARGE TRAP TRANSISTORS AND METHOD THEREOF CAPABLE OF STORING DATA BY TRAPPING OR DETRAPPING CHARGES
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机译：具有电荷陷阱晶体管的存储单元及其方法，该方法能够通过捕获或释放电荷来存储数据
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摘要
A memory cell includes a first charge trap transistor and a second charge trap transistor. The first charge trap transistor has a substrate, a first terminal coupled to a first bitline, a second terminal coupled to a signal line, a control terminal coupled to a wordline, and a dielectric layer formed between the substrate of the first charge trap transistor and the control terminal of the first charge trap transistor. The second charge trap transistor has a substrate, a first terminal coupled to the signal line, a second terminal coupled to a second bitline, a control terminal coupled to the wordline, and a dielectric layer between the substrate of the second charge trap transistor and the control terminal of the second charge trap transistor. Charges are either trapped to or detrapped from the dielectric layer of the first charge trap transistor when writing data to the memory cell.
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