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Methods and apparatus for performing product series operations in multiplier accumulator blocks

机译:在乘法累加器块中执行乘积运算的方法和装置

摘要

A specialized processing block on an integrated circuit includes a first and second arithmetic operator stage, an output coupled to another specialized processing block, and configurable interconnect circuitry which may be configured to route signals throughout the specialized processing block, including in and out of the first and second arithmetic operator stages. The configurable interconnect circuitry may further include multiplexer circuitry to route selected signals. The output of the specialized processing block that is coupled to another specialized processing block together with the configurable interconnect circuitry reduces the need to use resources outside the specialized processing block when implementing mathematical functions that require the use of more than one specialized processing block. An example for such mathematical functions include the implementation of scaled product sum operations and the implementation of Horner's rule.
机译:集成电路上的专用处理块包括第一和第二算术运算器级,耦合到另一个专用处理块的输出以及可配置的互连电路,可配置的互连电路可配置为在整个专用处理块中路由信号,包括在第一处理块的内部和外部进行路由和第二个算术运算符阶段。可配置互连电路可以进一步包括用于路由选择的信号的多路复用器电路。当实现需要使用多个专用处理块的数学功能时,与可配置互连电路一起耦合到另一专用处理块的专用处理块的输出减少了使用专用处理块之外的资源的需要。这种数学函数的示例包括按比例乘积和运算的实现和霍纳规则的实现。

著录项

  • 公开/公告号US10613831B2

    专利类型

  • 公开/公告日2020-04-07

    原文格式PDF

  • 申请/专利权人 ALTERA CORPORATION;

    申请/专利号US201816049855

  • 发明设计人 MARTIN LANGHAMMER;

    申请日2018-07-31

  • 分类号G06F7/523;G06F7/544;G06F7/57;

  • 国家 US

  • 入库时间 2022-08-21 11:26:43

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