4-k SRAM and 16-b multiply/accumulate DSP blocks have been designed and fabricated in complementary heterostructure GaAs. Both circuits operate from 1.5 V to below 0.9 V. The SRAM uses 28,272 transistors in an area of 2.44 mm/sup 2/. Cell size is 278 /spl mu/m/sup 2/ at 1.0-/spl mu/m gate length. Measured results show an access delay of 5.3 ns at 1.5 V and 15.0 ns at 0.9 V. At 0.9 V, the power dissipated is 0.36 mW. The CGaAs multiplier uses a 16-b modified Booth architecture with a 3-way 40-b accumulator. The multiplier uses 11,200 transistors in an area of 1.23 mm/sup 2/. Measured delay is 19.0 ns at 1.5 V and 44.7 ns at 0.9 V. At 0.9 V, current is less than 0.4 mA.
展开▼
机译：4 k SRAM和16 b乘法/累加DSP模块已经在互补异质结构GaAs中设计和制造。两种电路的工作电压均为1.5 V至0.9 V以下。SRAM使用28,272个晶体管，面积为2.44 mm / sup 2 /。栅长为1.0- / spl mu / m时，细胞大小为278 / spl mu / m / sup 2 /。测量结果表明，在1.5 V时的访问延迟为5.3 ns，在0.9 V时的访问延迟为15.0 ns。在0.9 V时，功耗为0.36 mW。 CGaAs乘法器使用16位修改的Booth架构和3位40位累加器。乘法器在1.23 mm / sup 2 /的面积中使用11,200个晶体管。在1.5 V时测得的延迟为19.0 ns，在0.9 V时测得的延迟为44.7 ns。在0.9 V时，电流小于0.4 mA。
展开▼
