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RISC-V RISC-V implemented processor with hardware acceleration supporting user defined instruction set and method therof
RISC-V RISC-V implemented processor with hardware acceleration supporting user defined instruction set and method therof
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机译：RISC-V RISC-V实现的处理器，具有硬件加速功能，支持用户定义的指令集和方法
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摘要
The present invention relates to a hardware high-speed computation combined reduced instruction set computing-V (RISC-V) based computation device for supporting a user-defined instruction set providing flexibility which configures a hardware high speed computation unit executing a user-defined function through a field programmable gate array (FPGA) in a single chip together with a RISC-V based computation device, executes general computation and user-defined computation in an instruction level, not a separate bus connection configuration, through a program using a RISC-V basic instruction set including a user-defined instruction set, and optionally changes the user-defined instruction set and a corresponding function and a method thereof. According to the present invention, in a manner similar to existing firmware update changing a software configuration, not a hardware configuration, new process structure modification including a new instruction set architecture (ISA) suitable for a specific purpose is performed, thereby providing an effect of implementing a special purpose computation unit in an instruction level without developing an exclusive application specific integrated circuit (ASIC) using a special purpose computation, which requires existing exclusive hardware, and the like.
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