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Testing electronic memories based on fault and test algorithm periodicity
Testing electronic memories based on fault and test algorithm periodicity
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机译：根据故障和测试算法周期性测试电子存储器
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摘要
An integrated circuit includes a memory and a memory test circuit, which when invoked to test the memory, is configured to generate one or more March tests applied to the memory. The memory test circuit is further configured to construct a table including a first index, a second index, and a first March test of the one or more March tests. The first index is associated with one or more families each characterized by a different length of the one or more March tests. The second index is associated with one or more mechanisms each characterized by a different property of the one or more March tests. The memory test circuit is further configured to generate a second March test from the first March test.
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