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Shallow Trench Isolation Area Having Buried Capacitor

机译：埋有电容器的浅沟槽隔离区

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摘要

A method of forming a semiconductor device includes providing a semiconductor substrate including a source/drain region, an active transistor region, and a substrate contact region coupled to a body region. A shallow trench isolation (STI) area is formed in a major surface of the semiconductor substrate in between the active transistor region and the substrate contact region. The method further includes at least partially burying at least one capacitor in the STI area.

机译：一种形成半导体器件的方法，包括提供半导体衬底，该半导体衬底包括源/漏区，有源晶体管区和耦合至主体区的衬底接触区。在有源晶体管区域和衬底接触区域之间的半导体衬底的主表面中形成浅沟槽隔离（STI）区域。该方法还包括将至少一个电容器至少部分地掩埋在STI区域中。

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公开/公告号US2017084607A1

专利类型
公开/公告日2017-03-23

原文格式PDF
申请/专利权人 INFINEON TECHNOLOGIES AG;
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申请/专利号US201615365237
发明设计人 HARTMUD TERLETZKI;
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申请日2016-11-30
分类号H01L27/06;H01L21/8234;H01L29/94;H01L29/06;H01L29/66;H01L21/762;H01L27/02;
国家 US
入库时间 2022-08-21 13:48:32

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