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Control of flatband voltages and threshold voltages in high-k metal gate stacks and structures for CMOS devices
Control of flatband voltages and threshold voltages in high-k metal gate stacks and structures for CMOS devices
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机译:高k金属栅极堆叠和CMOS器件结构中的平带电压和阈值电压的控制
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摘要
A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a high-k dielectric having a high dielectric constant greater than approximately 3.9, a germanium (Ge) material layer interfacing with the high-k dielectric, and a conductive electrode layer disposed above the high-k dielectric or the Ge material layer. The gate stack optimizes a shift of the flatband voltage or the threshold voltage to obtain high performance in p-FET devices.
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