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Erase verification circuitry for simultaneously and consecutively verifying a plurality of odd and even-numbered flash memory transistors and method thereof
Erase verification circuitry for simultaneously and consecutively verifying a plurality of odd and even-numbered flash memory transistors and method thereof
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机译：擦除验证电路，用于同时连续地验证多个奇数和偶数闪存晶体管及其方法
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摘要
Embodiments described herein generally relate to verifying that a FLASH memory has been erased. In an embodiment, a method of erase verifying a memory column of a FLASH memory includes applying a pass gate voltage to even numbered memory transistors while applying an erase verify voltage to the odd numbered memory transistors. Applying a string current to the memory column allows a probe to determine if the string current is successfully traversing the memory column, and thus verifying that the odd numbered memory transistors were erased. The even numbered memory transistors are verified in the following cycle.
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