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Computer system, computer-implemented method and computer program product for determining a pessimistic time response by an error tolerance mechanism

机译:通过容错机制确定悲观时间响应的计算机系统,计算机实现方法和计算机程序产品

摘要

The method involves determining running times of a check point component (12), a primary component (14), an alternate component (16) and a decider component (18) of a sensitive embedded system (10) with a fault tolerance mechanism in a flow path by the system. A failure mode is determined for one of the components, and a measuring point for the flow path is generated by combination of running times with the failure mode. A probability of occurrence of a mistake mode is computed, and a probability of occurrence of the measuring point is computed based on the probability of the failure mode. Independent claims are also included for the following: (1) a computer program product comprising a set of instructions for performing a method for determining pessimistic time performance of a fault tolerance mechanism (2) a computer system for determining pessimistic time performance of a fault tolerance mechanism.
机译:该方法涉及确定敏感嵌入式系统(10)中具有容错机制的检查点组件(12),主要组件(14),备用组件(16)和决策器组件(18)的运行时间。系统的流路。确定其中一个组件的故障模式,并通过将运行时间与故障模式相结合来生成流路的测量点。计算错误模式的发生概率,并基于故障模式的概率计算测量点的发生概率。还包括针对以下方面的独立权利要求:(1)一种计算机程序产品,包括一组指令,用于执行确定容错机制的悲观时间性能的方法的指令(2)用于确定容错的悲观时间性能的计算机系统机制。

著录项

  • 公开/公告号EP2544090A1

    专利类型

  • 公开/公告日2013-01-09

    原文格式PDF

  • 申请/专利权人 TECHNISCHE UNIVERSITAET KAISERSLAUTERN;

    申请/专利号EP20120003801

  • 发明设计人 HOEFIG KAI;

    申请日2012-05-14

  • 分类号G06F11/00;G06F11/36;G06F9/48;G06F11/14;

  • 国家 EP

  • 入库时间 2022-08-21 16:31:22

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