• 主题
高级搜索  >
历史搜索 清空历史
首页> 外国专利> MODE FOR CARRYING logical sum positional arguments analog signals term ni f (2n) and mi f (2n) of partial products in PRE adder fΣ ni amp; mi (2n) serializer MULTIPLIER fΣ (Σ) OF PROCEDURES FOR DOUBLE LOGICAL Differentiation d / dn + and d / dn- subtotals and shaping the resulting sum Si f (2n) in the position FORMAT

MODE FOR CARRYING logical sum positional arguments analog signals term ni f (2n) and mi f (2n) of partial products in PRE adder fΣ ni amp; mi (2n) serializer MULTIPLIER fΣ (Σ) OF PROCEDURES FOR DOUBLE LOGICAL Differentiation d / dn + and d / dn- subtotals and shaping the resulting sum Si f (2n) in the position FORMAT

机译：进行逻辑和位置自变量模拟信号的模式在PRE加法器fΣ[ni]和[mi]（2n）串行器中，乘积fΣ（Σ）的部分乘积的模拟信号项[ni] f（2n）和[mi] f（2n）对于双逻辑微分d / dn +和d / dn-小计，并将求和[Si] f（2n）整形为FORMAT位置

页面导航
  • 摘要
  • 著录项
  • 相似文献

摘要

FIELD: information technology.;SUBSTANCE: first and second intermediate sums are formed using logic elements OR and AND, and the next process for converting arguments is performed in two steps, the first step involving end-to-end activation of inactive arguments of the second intermediate sum with subsequent Boolean differentiation of only positive resultant arguments and the conditionally negative argument of that procedure is included in the structure of conditionally negative arguments of the result of end-to-end activation of inactive arguments of the second intermediate sum, through which the corresponding active arguments in the structure of the first intermediate sum are removed; a third position-sign intermediate sum is generated, in which the next inactive arguments are activated after the first active conditionally negative argument in the least bit and a fourth intermediate sum is generated for the second step for converting arguments, in which conditionally negative arguments undergo Boolean differentiation to generate only a positive argument of that procedure and then included in the resultant structure of arguments of the sum, where at the second step for converting arguments, arguments of the second intermediate sum undergo Boolean differentiation and the positive argument for local transfer of this procedure enables to avoid activation of inactive arguments of the third intermediate sum, and the conditionally negative argument for local transfer of this procedure from the resultant structure of arguments of the sum enable to exclude the active positive argument of the third intermediate sum and the resultant sum of analogue signals is generated in position format.;EFFECT: faster summation.
机译：领域：信息技术;实质：使用逻辑元素OR和AND形成第一和第二中间和，并且用于转换自变量的下一个过程分两个步骤执行，第一步涉及端到端激活非活动自变量。第二中间总和，其后仅是正结果自变量和该过程的条件负自变量的布尔微分，包括在第二中间总和的非活动自变量的端到端激活结果的条件负自变量的结构中，通过该结构，去除第一中间和结构中相应的有效自变量;产生第三位置符号中间和，其中在最小位中的第一活动条件负参数之后，激活下一个非活动参数，并为转换参数的第二步骤生成第四中间和，其中条件负参数经历布尔微分，仅生成该过程的正参数，然后包含在和参数的结果结构中，其中在第二步转换参数时，第二中间和的参数将进行布尔微分，而正参数用于局部转移该过程使得能够避免激活第三中间和的无效自变量，并且用于从该总和的自变量的结果结构中局部转移该过程的条件否定自变量使得能够排除第三中间和的有效正自变量及其结果。在pos中产生模拟信号的总和位置格式;效果：求和更快。

著录项

相似文献

  • 专利
  • 外文文献
获取专利

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号