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System and method for correcting systematic parametric variations on integrated circuit chips in order to minimize circuit limited yield loss
System and method for correcting systematic parametric variations on integrated circuit chips in order to minimize circuit limited yield loss
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机译：用于校正集成电路芯片上的系统参数变化以最小化电路限制的良率损失的系统和方法
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摘要
Disclosed are a system and a method of correcting systematic, design-based, parametric variations on integrated circuit chips to minimize circuit limited yield loss. Processing information and a map of a chip are stored. The processing information can indicate an impact, on a given device parameter, of changes in a value for a specification associated with a given process step. The map can indicate regional variations in the device parameter (e.g., threshold voltage). Based on the processing information and using the map as a guide, different values for the specification are determined, each to be applied in a different region of the integrated circuit chip during the process step in order to offset the mapped regional parametric variations. A process tool can then be selectively controlled to ensure that during chip manufacturing the process step is performed accordingly and, thereby to ensure that the regional parametric variations are minimized.
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