首页> 外国专利> 3D VERTICAL TYPE MEMORY CELL STRING WITH SHIELD ELECTRODE SURROUNDED BY A ISOLATION INSULATING LAYER STACK CAPABLE OF IMPROVING THE DEMAGNIFICATION PROPERTY AND THE PERFORMANCE OF A MOS(METAL OXIDE SEMICONDUCTOR) BASE FLASH MEMORY DEVICE, A MEMORY ARRAY USING THE SAME AND A MANUFACTURING METHOD THEREOF

3D VERTICAL TYPE MEMORY CELL STRING WITH SHIELD ELECTRODE SURROUNDED BY A ISOLATION INSULATING LAYER STACK CAPABLE OF IMPROVING THE DEMAGNIFICATION PROPERTY AND THE PERFORMANCE OF A MOS(METAL OXIDE SEMICONDUCTOR) BASE FLASH MEMORY DEVICE, A MEMORY ARRAY USING THE SAME AND A MANUFACTURING METHOD THEREOF

机译:记忆层的3D垂直型带屏蔽电极的垂直电池盒,绝缘层可改善放大率和基于氧化物的金属氧化物半导体存储器件的性能,一种存储方法

摘要

PURPOSE: A 3D vertical type memory cell string with shield electrode surrounded by a isolation insulating layer stack, a memory array using the same and a manufacturing method thereof are provided to solve the threshold voltage dissemination problem of stacks by injecting charges into the charge storage node in the isolation insulating layer stack as well as completely eliminate electrical interference which occurs in semiconductor bodies in both sides of each trench.;CONSTITUTION: Two or more electrode stacks are separated by one or more trenches at a certain distance on a semiconductor substrate(1) and are formed by repeatedly laminating an insulating layer and a conductive material layer(10) to the vertical direction by turns. A gate insulating layer stack includes a charge storage layer which is formed on the top and the side of each electrode stack and the separated space of the substrate. A semiconductor body(5) is formed on the gate insulating layer stack. A shield electrode(27) is formed by placing the isolation insulating layer for each trench on the semiconductor body. The isolation insulating layer includes the charge storage node.;COPYRIGHT KIPO 2011
机译:目的:提供一种具有被隔离绝缘层堆叠围绕的屏蔽电极的3D垂直型存储单元串,使用其的存储阵列及其制造方法,以通过将电荷注入电荷存储节点中来解决堆叠的阈值电压散布问题。隔离绝缘层堆叠中的绝缘层并完全消除了每个沟槽两侧的半导体本体中产生的电干扰。;组成:两个或多个电极堆叠在半导体衬底上以一定距离被一个或多个沟槽隔开(1绝缘层和导电材料层(10)在垂直方向上依次交替层压而成。栅绝缘层堆叠包括电荷存储层,该电荷存储层形成在每个电极堆叠的顶部和侧面以及基板的分离空间上。在栅极绝缘层堆叠上形成半导体本体(5)。通过为半导体本体上的每个沟槽放置隔离绝缘层来形成屏蔽电极(27)。隔离绝缘层包括电荷存储节点。; COPYRIGHT KIPO 2011

著录项

  • 公开/公告号KR101056113B1

    专利类型

  • 公开/公告日2011-08-10

    原文格式PDF

  • 申请/专利权人 SNU R&DB FOUNDATION;

    申请/专利号KR20100063958

  • 发明设计人 SHIN HYUNG CHEOL;LEE JONG HO;

    申请日2010-07-02

  • 分类号H01L27/115;H01L21/8247;H01L27/10;

  • 国家 KR

  • 入库时间 2022-08-21 17:49:56

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