首页> 外国专利> System and method to screen defect related reliability failures in CMOS SRAMS

System and method to screen defect related reliability failures in CMOS SRAMS

机译:在CMOS sram中筛选与缺陷相关的可靠性故障的系统和方法

摘要

A method for testing a semiconductor wafer. An array of probes is coupled to the semiconductor wafer. Then a voltage difference is applied across a plurality of adjacent metal line pairs (e.g., wordline and/or bitline pairs) of one or more SRAM arrays of at least one die. Application of the voltage difference induces failure of metal stringers or defects between the adjacent lines. Additionally, the voltage can be applied across respective pairs of substantially all parallel metal lines of the one or more SRAM arrays of more that one die of the semiconductor wafer.
机译:一种测试半导体晶片的方法。探针阵列耦合到半导体晶片。然后,在至少一个管芯的一个或多个SRAM阵列的多个相邻金属线对(例如,字线和/或位线对)上施加电压差。施加电压差会引起金属纵梁的故障或相邻线路之间的缺陷。另外,可在半导体晶片的一个以上裸片的一个或一个以上SRAM阵列的各对基本上所有平行金属线之间施加电压。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号