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Logic circuit redesign program, logic circuit redesign apparatus, and logic circuit redesign method

机译：逻辑电路再设计程序，逻辑电路再设计装置以及逻辑电路再设计方法

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摘要

A computer is allowed to execute an information acquisition process that acquires a file expressing information on pins used in respective ports provided in each block of a logic circuit to be redesigned and information indicating connection relationships between the ports (#2); execute a multiplexer disposition process that, based on the file, classifies pins of output ports of a block into a number of pin groups that is less than the number of pins, and disposes a multiplexer having a function to multiplex a signal output from each pin classified in the same pin group (#11, #13); and execute a demultiplexer disposition process that, based on that file, disposes a demultiplexer having a function to demultiplex signals that have been output from output ports of a block and multiplexed by the multiplexer, and a function to output each demultiplexed signal to input ports of respective input destination blocks (#12, #13).

机译：允许计算机执行信息获取过程，该信息获取过程获取文件，该文件表达关于在要重新设计的逻辑电路的每个块中提供的各个端口中使用的引脚的信息以及指示端口之间的连接关系的信息（＃ 2 ）;执行多路复用器布置过程，该过程基于该文件，将一个块的输出端口的插针分类为少于插针数量的多个插针组，并布置一个具有复用从每个插针输出的信号的功能的多路复用器分类在相同的引脚组（＃ 11，＃13 ）中;并执行基于该文件的多路分解器布置处理，该多路分解器布置有具有对从块的输出端口输出并由多路复用器多路复用的信号进行多路分解的功能，以及将每个经多路分解的信号输出至模块的输入端口的功能的解复用器。各自的输入目标块（＃ 12，＃13 ）。 展开▼

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公开/公告号US7735028B2

专利类型

公开/公告日2010-06-08

原文格式PDF

申请/专利权人 YOSHINORI SOEJIMA;YOSHIKATSU KOUHARA;HIROAKI SHIRAISHI;KOUICHI TANDA;TAKAKAZU TOKUNAGA;KOJI TAKATOMI;
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申请/专利号US20070902050

发明设计人 YOSHINORI SOEJIMA;YOSHIKATSU KOUHARA;HIROAKI SHIRAISHI;KOUICHI TANDA;TAKAKAZU TOKUNAGA;KOJI TAKATOMI;
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申请日2007-09-18

分类号G06F17/50;

国家 US

入库时间 2022-08-21 18:48:00

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