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Semiconductor device having shallow trench isolation structure comprising an upper trench and a lower trench including a void
Semiconductor device having shallow trench isolation structure comprising an upper trench and a lower trench including a void
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机译：具有包括上沟槽和下沟槽的浅沟槽隔离结构的半导体器件，该上沟槽和下沟槽包括空隙
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摘要
In one embodiment, a semiconductor device has an active region defined by an isolation layer formed inside an STI trench that includes an upper trench and a lower trench having a substantially curved cross-sectional profile under the upper trench so that the lower trench is in communication with the upper trench. Since the upper trench has a sidewall tapered with a positive slope, a good gap filling property can be obtained when filling the upper trench with an insulating layer. By forming a void in the lower trench, a dielectric constant at the bottom of the isolation layer is lower than a dielectric constant at an oxide layer, thereby improving the isolation property. The isolation layer includes a first insulating layer formed inside only the upper trench and covering an inner wall of the upper trench in the form of a spacer.
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