首页> 外国专利> METHOD FOR PROJECTING WAFER PRODUCT OVERLAY ERROR AND WAFER PRODUCT CRITICAL DIMENSION

METHOD FOR PROJECTING WAFER PRODUCT OVERLAY ERROR AND WAFER PRODUCT CRITICAL DIMENSION

机译:晶圆产品叠加误差和晶圆产品关键尺寸的投影方法

摘要

A method for projecting wafer product overlay error of the present invention is disclosed, the steps of the method comprises:(a) sample equipment overlay error data, equipment condition data, and actual wafer product overlay error data; (b) establish a neural network, the equipment overlay error data and the equipment condition data are inputs of the neural network, the generated output of the neural network is projected wafer product overlay error data, and the actual wafer product overlay error data is the target output of the neural network; and (c) set a mean square error target, train the neural network continuously until the mean square error of the neural network is no longer bigger than the mean square error target. Additionally a method for projecting wafer product critical dimension is also presented in the present invention.
机译:公开了本发明的晶片产品覆盖误差的预测方法,该方法的步骤包括:(a)对设备覆盖误差数据,设备状态数据和实际晶片覆盖误差数据进行采样。 (b)建立神经网络,设备覆盖误差数据和设备状态数据是神经网络的输入,神经网络的生成输出是投影晶片产品覆盖误差数据,而实际晶片产品覆盖误差数据为神经网络的目标输出; (c)设置均方误差目标,连续训练神经网络,直到神经网络的均方误差不再大于均方误差目标为止。另外,在本发明中还提出了一种用于投影晶片产品临界尺寸的方法。

著录项

  • 公开/公告号US2010049680A1

    专利类型

  • 公开/公告日2010-02-25

    原文格式PDF

  • 申请/专利权人 YU CHANG HUANG;WEN-HSIANG LIAO;

    申请/专利号US20080269296

  • 发明设计人 WEN-HSIANG LIAO;YU CHANG HUANG;

    申请日2008-11-12

  • 分类号G06F15/18;

  • 国家 US

  • 入库时间 2022-08-21 18:51:45

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