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Method for preparing Single-Electron Logic Transistor with Dual Gates operating at Room Temperature
Method for preparing Single-Electron Logic Transistor with Dual Gates operating at Room Temperature
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机译：在室温下工作的双栅极单电子逻辑晶体管的制备方法
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摘要
present invention is negative-positive photoresist and the photoresist pattern width of the nanowire over a defined area and nanowires dual operating at room temperature to form the two gates can control the potential of the quantum dot to the right and left sides of the nanowire region through the selection ratio of the etching caused by the height difference of negative photoresist and the nanowire region other than the gate region is present on the single-electron logic device It relates to a process for the production of. In order to achieve this, (a) etching the semiconductor layer of a substrate having an insulating layer between the semiconductor layer and defining a channel region; (B) forming an oxide film on the channel region; (C) forming a negative photoresist pattern on the oxide film; (D) forming a positive photoresist pattern on a vertical sound photosensitive film pattern; (E) forming a nanowire region by etching the oxide layer and the semiconductor layer exposed by the positive photoresist pattern; (F) forming a quantum dot to form an oxide film on both sides of the silicon layer; (G) forming a gate on top of the negative photosensitive film pattern; (H) a step of coating a positive photosensitive film on the top side rotates in the whole of the semiconductor layer; (I) etching the photoresist from the top of the thin thickness speech by removing the two gates to the left and right around the negative photosensitive film pattern; And, (j) depositing an oxide film and a step of forming a gate metal over all of the negative photosensitive area.
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