Logic circuit, system for reducing a clock skew, and method for reducing a clock skew

• 1. 3D堆叠存储器、时钟偏斜消除方法及时钟偏斜消除电路 [P] . 中国专利： CN111179987A . 2020-05-19
• 2. 一种适用于VLSI片上时钟系统的偏斜检测和去偏斜调节电路 [P] . 中国专利： CN103248341B . 2016.01.20
• 3. Logic circuit, system for reducing a clock skew, and method for reducing a clock skew [P] . 美国专利： US7495476B2 . 2009-02-24

  机译： 逻辑电路，减少时钟偏斜的系统以及减少时钟偏斜的方法

• 4. LOGIC CIRCUIT, SYSTEM FOR REDUCING A CLOCK SKEW, AND METHOD FOR REDUCING A CLOCK SKEW [P] . 美国专利： US2008036498A1 . 2008-02-14

  机译： 逻辑电路，减少时钟偏斜的系统以及减少时钟偏斜的方法

• 5. Logic circuit, system for reducing a clock skew, and method for reducing a clock skew [P] . 美国专利： US2006055423A1 . 2006-03-16

  机译： 逻辑电路，减少时钟偏斜的系统以及减少时钟偏斜的方法

• 1. DESIGN OF TWO-PHASE SINUSOIDAL POWER CLOCK AND CLOCKED TRANSMISSION GATE ADIABATIC LOGIC CIRCUIT [J] . Wang Pengjun, Yu Junjun 电子科学学刊（英文版） . 2007,第002期
• 2. DESIGN OF TWO-PHASE SINUSOIDAL POWER CLOCK AND CLOCKED TRANSMISSION GATE ADIABATIC LOGIC CIRCUIT [J] . Wang, Pengjun, Yu, 电子科学学刊：英文版 . 2007,第002期
• 3. The clock system for LHAASO WCDA based on reduced White Rabbit [J] . LI Cheng, LIU Shubin, SHANG Linfeng, 核技术（英文版） . 2012,第004期
• 4. A Clock Skewing Strategy to Reduce Power and Area of ASIC Circuits [C] . Niranjan Kulkarni, Aykut Dengi, Sarma Vrudhula ACM/EDAC/IEEE Design Automation Conference . 2017
• 5. Current-Mode Clocking and Synthesis Considering Low-Power and Skew [D] . Islam, Riadul. 2017
• 6. Rigorously modeling self-stabilizing fault-tolerant circuits: An ultra-robust clocking scheme for systems-on-chip [O] . Danny Dolev, Matthias Függer, Markus Posch, -1
• 7. Selectively clocked skewed logic (SCSL): A robust low-power logic style for high-performance applications [O] . Naran Sirisantana, Aiqun Cao, Shawn Davidson, 2001
• 8. Adaptive Method for Reducing Clock Skew in an Accumulative Z-Axis Interconnect System [R] . Bolotin, G. , Boyce, L. 1997

• 1. 同步电路设计中CLOCK SKEW的分析 [J] . 康军 ,黄克勤 ,张嗣忠 . 电子器件 . 2002,第004期
• 2. Study of “Radiation Effects of Nuclear High Energy Particles” on Electronic Circuits and Methods to Reduce Its Destructive Effects [J] . Omid Zeynali ,Daryoush Masti ,Maryam Nezafat . 现代物理（英文） . 2011,第12期
• 3. 时钟偏斜补偿电路设计 [C] . 曾献君 ,陈亮 ,罗礼 . 第十届计算机工程与工艺全国学术年会 . 2006
• 4. 超大规模高频低偏斜时钟树设计方法研究 [A] . 刘雅 . 2020