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Timing convergence, efficient algorithm to automate swapping of standard devices with low threshold-voltage devices

机译:定时收敛,高效算法,可自动将标准设备与低阈值电压设备交换

摘要

A method for optimizing low threshold-voltage (Vt) devices in an integrated circuit design. The method includes identifying paths and nodes within the integrated circuit design, determining node overlap within the integrated circuit design, calculating possible solutions for addressing timing violations within the integrated circuit design, choosing a solution for addressing timing violations, inserting low Vt devices at particular nodes of the integrated circuit design, and repeating the calculated possible solutions wherein choosing a solution and inserting low Vt devices at particular nodes to address timing violations within the integrated circuit design.
机译:一种在集成电路设计中优化低阈值电压(V t )器件的方法。该方法包括识别集成电路设计内的路径和节点,确定集成电路设计内的节点重叠,计算用于解决集成电路设计内的时序违规的可能解决方案,选择用于解决时序违规的解决方案,插入低V t集成电路设计的特定节点上的设备,并重复计算的可能解决方案,其中选择一种解决方案,并在特定节点处插入低V t 设备以解决集成电路设计中的时序冲突。

著录项

  • 公开/公告号US7254795B2

    专利类型

  • 公开/公告日2007-08-07

    原文格式PDF

  • 申请/专利权人 UMESH NAIR;TOSHINARI TAKAYANAGI;

    申请/专利号US20050152929

  • 发明设计人 UMESH NAIR;TOSHINARI TAKAYANAGI;

    申请日2005-06-15

  • 分类号G06F17/50;

  • 国家 US

  • 入库时间 2022-08-21 21:00:32

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