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Evaluation method using a TEG, a method of manufacturing a semiconductor device having a TEG, an element substrate and a panel having the TEG, a program for controlling dosage and a computer-readable recording medium recoding the program
Evaluation method using a TEG, a method of manufacturing a semiconductor device having a TEG, an element substrate and a panel having the TEG, a program for controlling dosage and a computer-readable recording medium recoding the program
The reliability of a GOLD structure TFT depends on an impurity concentration in its gate-overlapped region. Thus, it is an object of the present invention to obtain a resistance distribution corresponding to a tapered shape of a gate electrode in a gate-overlapped region. According to the present invention, plural TEGs are manufactured as Lov resistance monitors in which mask alignment is misaligned with several μm interval to perform a resistance measurement on each of the TEGs. Consequently, a resistance distribution corresponding to a tapered shape can be obtained in a channel forming region, a gate-overlapped region and a source/drain region.
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