首页> 外国专利> FLOOR PLAN DESIGN PROGRAM, FLOOR PLAN DESIGN DEVICE, AND DESIGN METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT

FLOOR PLAN DESIGN PROGRAM, FLOOR PLAN DESIGN DEVICE, AND DESIGN METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT

机译：平面图设计程序，平面图设计装置以及半导体集成电路的设计方法

页面导航

摘要
著录项
相似文献

摘要

PPROBLEM TO BE SOLVED: To provide a design method by which design TAT (turn around time) of layout design of a semiconductor integrated circuit including a plurality of blocks is reduced. PSOLUTION: A floor plan of semiconductor integrated circuit is designed using a netlist including a circuit block data of a plurality of circuit blocks, and connection data between blocks of a plurality of circuit blocks; timing constraint conditions to each connection between circuit blocks; and relation data indicating relations between wire length and timing. A 1st step is a step S11 to arrange the circuit block. A 2nd step is a step S12 which calculates estimated wire length between circuit blocks, by using positions to which circuit blocks are arranged and the above connection data. A 3rd step is a step S14 which determines whether the estimated wire length fulfills the timing constraint conditions based on the relation data. A 4th step ia a step S17 which displays determination result determined at the 3rd step. PCOPYRIGHT: (C)2007,JPO&INPIT

机译：

要解决的问题：提供一种设计方法，通过该设计方法可以减少包括多个模块的半导体集成电路的布局设计的设计TAT（周转时间）。

解决方案：半导体集成电路的平面图是使用网表设计的，该网表包括多个电路块的电路块数据以及多个电路块的块之间的连接数据。电路块之间每个连接的时序约束条件;表示线长与时间的关系的关系数据。第一步骤是布置电路块的步骤S11。第二步骤是步骤S12，其通过使用布置电路块的位置和上述连接数据来计算电路块之间的估计导线长度。第三步骤是步骤S14，其基于关系数据确定所估计的导线长度是否满足时序约束条件。第四步骤是步骤S17，其显示在第三步骤中确定的确定结果。

版权：（C）2007，日本特许厅＆INPIT 展开▼

著录项

公开/公告号JP2006323643A

专利类型
公开/公告日2006-11-30

原文格式PDF
申请/专利权人 NEC ELECTRONICS CORP;
展开▼

申请/专利号JP20050146548
发明设计人 OKABE HIDEYUKI;
展开▼

申请日2005-05-19
分类号G06F17/50;H01L21/82;H01L21/822;H01L27/04;
国家 JP
入库时间 2022-08-21 21:10:30

相似文献

专利
外文文献
中文文献