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2-Level Cache Memory System Reducing Data Transfer Time
2-Level Cache Memory System Reducing Data Transfer Time
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机译：2级高速缓存存储系统，减少了数据传输时间
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摘要
PURPOSE: A 2-level cache memory system is provided to virtually include a level 1 cache so that it can implement a DTS for a cache synchronization in a multimedia system and reduce a data transmission time. CONSTITUTION: A 2-level cache memory system comprises a level 1 instruction cache(310), a level 1 data cache(320), a first multiplexor, a second multiplexor, a level 2 cache(370), a victim buffer(360), a victim controller(390) and a third multiplexor. The level 1 instruction cache(310) stores a plurality of instructions connected to tags. The tags are connected by an instruction address bus, and the instructions connected by an instruction bus. The level 1 data cache(320) stores a plurality of data connected to the tags. The first multiplexor selectively outputs the tags of the level 1 instruction cache(310) or the tags of the level 1 data cache(320) in response to a first selection signal. The second multiplexor selectively the instructions of the level 1 instruction cache(310) or the data of the level 1 data cache(320) in response to the first selection signal. The level 2 cache(370) stores instructions or data connected to the tags. The victim buffer(360) buffers a plurality of victim instructions and data generated from the level 1 instruction cache(310), the level 1 data cache(320) or the level 2 cache(370). The victim controller(390) generates a victim by comparing state bits of the level 1 instruction cache(310), the level 1 data cache(320) or the level 2 cache(370), and transmits the victim data, buffered in the buffer(360), to the level 2 cache(370) or a main memory.
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