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METHOD FOR PERFORMANCE DRIVEN HIGH LEVEL SYNTHESIS FROM BEHAVIORAL DISCRIPTION TO HIERARCHICAL FIELD PROGRAMMABLE GATE ARRAY
METHOD FOR PERFORMANCE DRIVEN HIGH LEVEL SYNTHESIS FROM BEHAVIORAL DISCRIPTION TO HIERARCHICAL FIELD PROGRAMMABLE GATE ARRAY
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机译：从行为描述到分层场可编程门阵列的性能驱动高水平合成的方法
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摘要
The present invention obtains the component arrangement information on the basis of information obtained FPGA, the component placement information relates to a high-level synthesis method for performance of hierarchical FPGA that can reduce the delay time of the overall system by, comprising the steps of: obtaining information of a selected target FPGA architecture (target architecture); The data flow graph (DFG: data flow graph) receives the, components determining the initial clock (clock) based on the delay time of a (functional unit) and binding (binding) and further comprising; Using the information of the acquired FPGA obtain a component arrangement information to be placed on the FPGA, and the component arrangement information acquired by the yirueojim by performing a scheduling based on, it is possible to reduce the overall system delay, connection lines can be treated more effectively delay.
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