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SRAM ARRAY, SRAM CELL, MICROPROCESSOR, METHOD, AND SRAM MEMORY (SRAM MEMORY AND MICROPROCESSOR COMPRISING LOGIC PORTION REALIZED ON HIGH-PERFORMANCE SILICON SUBSTRATE AND SRAM ARRAY PORTION, INCLUDING FIELD EFFECT TRANSISTOR HAVING LINKED BODY AND METHOD FOR MANUFACTURING THEM)
SRAM ARRAY, SRAM CELL, MICROPROCESSOR, METHOD, AND SRAM MEMORY (SRAM MEMORY AND MICROPROCESSOR COMPRISING LOGIC PORTION REALIZED ON HIGH-PERFORMANCE SILICON SUBSTRATE AND SRAM ARRAY PORTION, INCLUDING FIELD EFFECT TRANSISTOR HAVING LINKED BODY AND METHOD FOR MANUFACTURING THEM)
PROBLEM TO BE SOLVED: To provide an SRAM memory and a microprocessor, comprising a logic portion formed on a silicon substrate and an SRAM array portion.;SOLUTION: The SRAM array has a body region, where at least one pair of neighboring NFETs of the SRAM cell is linked in a leakage path diffusion region 338 under shallow source/drain region 334, the leakage path diffusion region extends from the bottom of the source/drain diffusion to an embedded oxide layer 320; and at least one pair of PFETs of the neighboring SRAM cells has a body region 336, linked in a similar leakage path diffusion region under neighboring source/drain diffusion. The logic circuit portion of the microprocessor has a floating body region and an NFET, formed in a crystal orientation SOI silicon region 330 and a PFET formed in a crystal orientation bulk silicon region, and the SRAM memory portion has an NFET, formed in the crystal orientation SOI silicon region and a PFET formed in the crystal orientation silicon region.;COPYRIGHT: (C)2006,JPO&NCIPI
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