首页> 外国专利> Drain to source transient disturbance detector for thyristor transient latch up measurement has pulse generator connected to p and n well CMOS test structure

Drain to source transient disturbance detector for thyristor transient latch up measurement has pulse generator connected to p and n well CMOS test structure

机译:用于晶闸管瞬态闩锁测量的漏源瞬态干扰检测器,脉冲发生器连接到p和n阱CMOS测试结构

摘要

A drain to source transient disturbance detector has a four layer CMOS (Complementary Metal Oxide Silicon) test structure with n+ and p+ diffusion in a p-well and p+ and n= diffusion in an n-well both in a p-substrate connected between a pulse generator creating disturbances and a current sensor detector. Includes INDEPENDENT CLAIMs for bipolar and biCMOS (bipolar Complementary Metal Oxide Silicon) technology versions and for capacitive or diode connection of the pulse generator.
机译:漏极至源极瞬态扰动检测器具有四层CMOS(互补金属氧化物硅)测试结构,在p阱中的n +和p +扩散以及在n阱中的p +和n =扩散都在连接在硅衬底之间的p衬底中。产生干扰的脉冲发生器和电流传感器检测器。包括针对双极和biCMOS(双极互补金属氧化物硅)技术版本以及脉冲发生器的电容或二极管连接的独立声明。

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