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Drain to source transient disturbance detector for thyristor transient latch up measurement has pulse generator connected to p and n well CMOS test structure
Drain to source transient disturbance detector for thyristor transient latch up measurement has pulse generator connected to p and n well CMOS test structure
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机译:用于晶闸管瞬态闩锁测量的漏源瞬态干扰检测器,脉冲发生器连接到p和n阱CMOS测试结构
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摘要
A drain to source transient disturbance detector has a four layer CMOS (Complementary Metal Oxide Silicon) test structure with n+ and p+ diffusion in a p-well and p+ and n= diffusion in an n-well both in a p-substrate connected between a pulse generator creating disturbances and a current sensor detector. Includes INDEPENDENT CLAIMs for bipolar and biCMOS (bipolar Complementary Metal Oxide Silicon) technology versions and for capacitive or diode connection of the pulse generator.
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