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Logic circuit optimizing method, logic circuit optimizing device and logic circuit composing device

机译：逻辑电路优化方法，逻辑电路优化装置及逻辑电路构成装置

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摘要

A dividing flip-flop FF2 is inserted in a cluster C of which the cluster length exceeds a predetermined cluster length. The flip-flop inserted cluster C is re-clustered, generating subdivided clusters C1 and C2. Therefore, the degree of freedom is increased in allocating clusters to a variable logic element such as an FPGA in a logical emulation device.

机译：将分割触发器FF 2 插入到簇长超过预定簇长的簇C中。触发器插入的群集C被重新群集，生成细分的群集C 1 和C 2 。因此，在将集群分配给诸如逻辑仿真设备中的FPGA之类的可变逻辑元件时，自由度增加了。 展开▼

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公开/公告号US2004237055A1

专利类型

公开/公告日2004-11-25

原文格式PDF

申请/专利权人 KIMURA TOMOO;ISHIDA KENICHI;INOMOTO TOMOYUKI;
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申请/专利号US20040773276

发明设计人 TOMOO KIMURA;KENICHI ISHIDA;TOMOYUKI INOMOTO;
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申请日2004-02-09

分类号G06F17/50;

国家 US

入库时间 2022-08-21 22:24:14

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