首页>
外国专利>
Super scalar type microprocessor and data processing device
Super scalar type microprocessor and data processing device
展开▼
机译：超标量型微处理器和数据处理装置
展开▼
页面导航
摘要
著录项
相似文献
摘要
The high-performance, RISC core based microprocessor architecture permits concurrent execution of instructions obtained from memory through an instruction prefetch unit having multiple prefetch paths allowing for the main program instruction stream, a target conditional branch instruction stream and a procedural instruction stream. The target conditional branch prefetch path allows both possible instruction streams for a conditional branch instruction to be prefetched. The procedural instruction prefetch path allows a supplementary instruction stream to be accessed without clearing the main or target prefetch buffers. Each instruction set includes a plurality of fixed length instructions. An instruction FIFO is provided for buffering instruction sets in a plurality of instruction set buffers including a first buffer and a second buffer. An instruction execution unit including a register file and a plurality of functional units is provided with an instruction control unit capable of examining the instruction sets within the first and second buffers and scheduling any of the instructions for execution by available functional units. Multiple data paths between the functional units and the register file allow multiple independent accesses to the register file by the functional units as necessary for the execution of the respective instructions. The register file includes an additional set of temporary data registers. These temporary data registers are utilized by the instruction execution control unit to receive data processed by the functional units by the out-of-order execution of instructions in advance of the completed execution of a conditional branch instruction or any instruction that requires additional functional unit processing cycles to complete. The data stored in the temporary data registers is selectively held, cleared or retired to the register file depending on the actual state of the instruction stream at the point where all prior instructions have been executed. IMAGE
展开▼
