首页> 外国专利> MEMORY CELL, FABRICATING METHOD THEREOF, MULTILAYER MEMORY, HIGH CAPACITY STORING APPARATUS, INTEGRATED CIRCUIT, SUBSTRATE CARRYING MICROELECTRONIC APPARATUS, ELECTRONIC DEVICE, MAGNETIC TUNNEL JUNCTION MEMORY CELL AND METHOD FOR USING MEMORY CELL WITH MAGNETIC STORING DEVICE AND TUNNEL JUNCTION DETECTING DEVICE TO MORE EFFECTIVELY ISOLATE MAGNETIC TUNNEL JUNCTION MEMORY CELL AND REDUCE DEFECT GENERATION RATIO OF JUNCTION PART

MEMORY CELL, FABRICATING METHOD THEREOF, MULTILAYER MEMORY, HIGH CAPACITY STORING APPARATUS, INTEGRATED CIRCUIT, SUBSTRATE CARRYING MICROELECTRONIC APPARATUS, ELECTRONIC DEVICE, MAGNETIC TUNNEL JUNCTION MEMORY CELL AND METHOD FOR USING MEMORY CELL WITH MAGNETIC STORING DEVICE AND TUNNEL JUNCTION DETECTING DEVICE TO MORE EFFECTIVELY ISOLATE MAGNETIC TUNNEL JUNCTION MEMORY CELL AND REDUCE DEFECT GENERATION RATIO OF JUNCTION PART

机译：存储器单元，其制造方法，多层存储器，高容量存储设备，集成电路，基板携带微电子设备，电子设备，磁隧道结存储单元以及使用该存储单元的存储器的方法和用于存储设备的方法磁性隧道连接记忆细胞及减小连接部位的缺陷产生率

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PURPOSE: A method for fabricating a memory cell is provided to more effectively isolate a magnetic tunnel junction memory cell and reduce a defect generation ratio by a relatively simple process. CONSTITUTION: A substrate is prepared. The first metal layer is deposited, and the first metal conductor is patterned and etched. The first ferromagnetic layer(80) is deposited, patterned and etched. An interlayer dielectric(35) is deposited. A via opening(65) is etched through the interlayer dielectric at least partially aligned with the first metal conductor to expose a part of the first ferromagnetic layer. A thin tunnel junction oxide layer(70) is formed on the at least exposed part of the first ferromagnetic layer. The second ferromagnetic layer(60) is deposited to fill at least the via opening. The surface of the resultant structure is planarized to the surface of the interlayer dielectric. The second metal layer is deposited. The second metal conductor at least partially aligned with the via opening filled with the second ferromagnetic layer is patterned and etched.

机译：目的：提供一种制造存储单元的方法，以通过相对简单的工艺更有效地隔离磁隧道结存储单元并降低缺陷产生率。组成：准备好基材。沉积第一金属层，并对第一金属导体进行构图和蚀刻。沉积，图案化和蚀刻第一铁磁层（80）。沉积层间电介质（35）。蚀刻穿过与第一金属导体至少部分对准的层间电介质的通孔开口（65），以暴露出第一铁磁层的一部分。在第一铁磁层的至少暴露的部分上形成薄的隧道结氧化物层（70）。沉积第二铁磁层（60）以至少填充通孔开口。将所得结构的表面平坦化至层间电介质的表面。沉积第二金属层。构图和蚀刻与填充有第二铁磁层的通孔开口至少部分对准的第二金属导体。

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公开/公告号KR20040078883A

专利类型
公开/公告日2004-09-13

原文格式PDF
申请/专利权人 HEWLETT-PACKARD DEVELOPMENT COMPANY L.P.;
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申请/专利号KR20040014558
发明设计人 FRICKE PETER;KOLL ANDREW;VANBROCKLIN ANDREW L.;
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申请日2004-03-04
分类号H01L27/115;H01L27/10;H01L27/105;
国家 KR
入库时间 2022-08-21 22:48:08

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