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Clock signal conversion circuit used with phase-locked loop circuit has 2 difference amplifiers each converting input clock signal pair into unsymmetrical clock signals
Clock signal conversion circuit used with phase-locked loop circuit has 2 difference amplifiers each converting input clock signal pair into unsymmetrical clock signals
The circuit has a pair of difference amplifiers (20,22), respectively having 2 n-channel field effect transistors (N1,N2) or 2 p-channel field effect transistors (P3,P4), each amplifier receiving an input clock signal pair (CLK,NCLK) at its difference inputs and providing an unsymmetrical clock signal at its output. The operating points of the difference amplifiers are controlled by respective bias circuits (N5,N6,N7; P5,P6), their output signals combined to provide an unsymmetrical output clock signal (A-CLK).
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