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Design validation method for integrated system chip circuit, involves validating entire design using simulation test banks of complete system chip and execution of application
Design validation method for integrated system chip circuit, involves validating entire design using simulation test banks of complete system chip and execution of application
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机译：集成系统芯片电路的设计验证方法，包括使用完整系统芯片的仿真测试库验证整个设计并执行应用程序
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摘要
Interfaces between individual modules, chip internal buses of modules and connection logic are verified by simulation test banks designed by system chip development engineer and using user programmable gate array or emulation of logic. Time control of module at various critical path level is verified and entire design is validated by simulation test banks of complete system chip and application execution. An Independent claim is also included for integrated system chip circuit.
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