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Multi-layer silicon nitride deposition method for forming low oxidation temperature thermally oxidized silicon nitride/silicon oxide (no) layer
Multi-layer silicon nitride deposition method for forming low oxidation temperature thermally oxidized silicon nitride/silicon oxide (no) layer
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机译：用于形成低氧化温度的热氧化氮化硅/氧化硅（无）层的多层氮化硅沉积方法
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摘要
A method for forming a silicon nitride/silicon oxide (NO) layer within a microelectronics fabrication, and the microelectronics fabrication having the silicon nitride/silicon oxide (NO) layer formed therein. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a first silicon nitride layer through a first deposition method. There is then formed upon the first silicon nitride layer a second silicon nitride layer through a second deposition method. Finally, there is annealed thermally in an oxidizing environment the first silicon nitride layer and the second silicon nitride layer to form therefrom a silicon nitride/silicon oxide (NO) layer. The silicon nitride/silicon oxide (NO) layer may be formed with optimized resistivity properties at a reduced thermal annealing temperature and/or a reduced thermal annealing exposure time in comparison with an otherwise equivalent silicon nitride/silicon oxide (NO) layer formed through thermal annealing a single silicon nitride layer of thickness equivalent to the thickness of the first silicon nitride layer plus the thickness of the second silicon nitride layer. When formed upon a silicon oxide dielectric layer in turn formed upon a first capacitor plate within a capacitor within an integrated circuit, there may be formed employing the silicon nitride/silicon oxide (NO) layer a silicon oxide/silicon nitride/silicon oxide (ONO) capacitive dielectric layer.
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