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Designing a processor architecture with multiple sources supplying bank address values and designing the same
Designing a processor architecture with multiple sources supplying bank address values and designing the same
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机译：设计具有多个提供库地址值的源的处理器体系结构，并设计相同的
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摘要
A processor architecture design is disclosed that includes multiple sources capable of encoding multiple addressing modes and generating bank address values. The processor architecture design includes a central processing unit (CPU) that executes the instruction set. The data memory is coupled to the CPU. The data memory stores and transmits data from the CPU. The data memory is divided into a plurality of banks, one of which is dedicated to general purpose and specific function registers. A selection circuit is coupled to the data memory. The selection circuit selects one of the multiple sources generating the bank address value. A selection circuit register is coupled to the selection circuit. The bank select register supplies the bank address value for the instruction to be executed directly in the short addressing mode. The instruction register directly supplies the bank address value for the instruction to be executed in the long addressing mode, supplies the intra-bank register address for the instruction to be executed in the direct short addressing mode, and is coupled to the selection circuit.
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