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Method for testing a memory chip subdivided into cell fields while a computer is in operation while observing real-time conditions
Method for testing a memory chip subdivided into cell fields while a computer is in operation while observing real-time conditions
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机译:在观察实时状况的同时在计算机运行时测试细分为单元字段的存储芯片的方法
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摘要
The method involves testing a memory chip which is subdivided in cells (ZF) which are arranged in a matrix of line areas (ZB) and column areas (SB). A first line area is selected, and if the contents of this line area are used by an application program, the contents are copied into a free second line area, and an addressing of the application program is modified accordingly. A Franklin-test is executed for all cells (ZF) of the first line area. Two cells of the line area are selected, and a Nair-test is performed on an arbitrary cell line (ZZ) of both selected cells. The Nair-test is repeated with another pair of cells, until all possible combinations of cell pairs are tested. A Nair test is performed on an arbitrary cell column, limited to the selected first line area, and the entire process is first executed for all line areas of the memory chip, and then for all respective column areas.
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