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IGBT device with platinum lifetime control and reduced gaw
IGBT device with platinum lifetime control and reduced gaw
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机译：IGBT器件，具有铂金寿命控制和降低的偏移
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摘要
For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N- layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (˜10.sup.14 /cm.sup.3) to block reverse bias voltage. The N+ layer is 20 &mgr;m thick and doped below ˜10. sup.17 /cm.sup. 3 but above the N- doping to enhance output impedance and reduce gain at high V.sub.ce conditions. Or the N+ layer is formed with a thin (˜5 &mgr;m) highly doped ( 10.sup.17 /cm.sup.3) layer and a thick ( 20 &mgr;m) layer of ˜10.sup.16 /cm.sup.3 doping. A platinum dose of 10.sup.13 to 10.sup.16 /cm.sup.3 is ion implanted and diffused into the silicon to effect lifetime control. Gate and source contacts and body and source diffusions have an inter-digitated finger pattern with complementary tapers to minimize current crowding and wide gate buses to minimize signal delay. P+ doping beneath and marginally surrounding the gate pads and main gate bus negates breakdown conditions in widely spaced body regions and convex localities at the source finger end. Wide secondary gate buses parallel to the gate fingers have a P+ doped central stripe and transverse shorting bars spaced along their length. A non- polarizable PECVD passivation film of low phosphorus PSG and nitride or oxynitride or of oxynitride alone is made by controlling ionized gas residence time, silane partial pressure, and oxygen ratio during deposition, to minimize incorporation of Si--H into the film.
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机译：对于IGBT，MCT或类似器件，衬底形成有P +，N +和N-层以及PN扩散，以在N-层中定义体区和源极区，并在上表面定义MOS门控沟道。调整N层的尺寸和掺杂（〜10×14 / cm×3）以阻挡反向偏置电压。 N +层的厚度＞20μm，并且掺杂到约10以下。 sup.17 /cm.sup。 3，但高于N掺杂，以提高输出阻抗并在高V条件下降低增益。或者，N +层由高掺杂的薄（〜5μm）（＞10μm17 / cm 3）和厚的（＞20μm）层（〜10μm）形成。 16 /cm.sup.3掺杂。将离子剂量为10×13至10×16 / cm 3的铂注入并扩散到硅中，以实现寿命控制。栅极和源极接触以及体和源极扩散具有相互交叉的指状图案，具有互补的锥度，以最大程度地减少电流拥挤，而宽的栅极总线则可以最大程度地减少信号延迟。在栅极焊盘和主栅极总线下方并略微围绕栅极焊盘和主栅极总线的P +掺杂消除了宽间隔的主体区域和源极指端凸形区域中的击穿条件。平行于栅极指的宽辅助栅极总线具有P +掺杂的中心条纹和沿其长度方向隔开的横向短路棒。通过控制沉积过程中的离子化气体停留时间，硅烷分压和氧比，可最大程度地减少Si-H掺入膜中，从而制成低磷PSG和氮化物或氮氧化物或仅氮氧化物的不可极化PECVD钝化膜。
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