PURPOSE:To shorten a program itself and to prevent the deterioration of the program executing time by using the output delayed an amount equivalent to the executing time of a single instruction of a CPU and an address received from the CPU to designate the addresses of an instruction memory and a space code memory. CONSTITUTION:A real address bus 16 of (n+1) bits consists of an address signal 14 (lower lever n bits) given from a CPU 10 and the output (one higher level bit) of a DFF 13 and is connected to the address input terminals of a space code memory 11 and an instruction memory 12 respectively. The DFF 13 is reset by a resetting signal 19 together with the CPU 10 and outputs '0' to an output 20. At the same time, the DFF 13 stores the contents of an outer 17 of the memory 11 by an instruction executing timing clock 15 outputted from the CPU 10 and then outputs these stored contents to the bus 16 after an approximately single executing cycle. The memory 12 outputs the instruction stored in an address designated by the contents of the bus 16 to the CPU 10 via an instruction bus 18. In such a way, a program itself is shortened and also the program executing time is shortened.
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