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Synchronising circuit for timing signal using cascaded flip=flops - uses one flip=flop as polarity detector of signal and connects to second via delay by logic
Synchronising circuit for timing signal using cascaded flip=flops - uses one flip=flop as polarity detector of signal and connects to second via delay by logic
The synchronising circuit for a step shaped change of state can take place randomly, with a timing signal. It consists of two flip-flop circuits (FF1 and 2) which are connected in cascade. The first flip-flop is designed as a detector which will produce a selector signal indicative of the polarity of the timing signal. The first slip-flop is coupled to delay networks (L1,L2) which are intended to delay the transmission of the change of state to the second flip-flop. The delays are set selectively by control logics (1,2,3) which are independent of the selector signal. The first flip-flop has two separate output puts and the selector signal is characterised by the potential pattern of the two outputs.
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