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INTEGRATED SCALE STRUCTURES WITH INDIVIDUAL SELF-EDUCATING BARRIERS

机译:具有个别自我教育障碍的综合规模结构

摘要

Integrated circuit structures with undressed self-forming barriers and procedures for the production of integrated circuit structures with undressed self-forming barriers are described. For an example, an integrated circuit structure contains a dielectric material above a substrate. An intermediate connection structure is located in a ditchn in the dielectric material. The interlinking structure includes a conductive filling material and a two-dimensional (2D) crystalline lining. The crystalline 2D lining is in direct contact with the dielectric material and with the conductive filling material. The crystalline 2D lining contains the same metal specifications as the conductive filling material.
机译:描述了具有脱衣服的自成形屏障的集成电路结构和用于生产具有脱衣服的自成形屏障的集成电路结构的程序。例如,集成电路结构包含基板上方的介电材料。中间连接结构位于介电材料中的沟中。互连结构包括导电填充材料和二维(2D)晶体衬里。结晶2D衬里与介电材料和导电填充材料直接接触。结晶2D衬里含有与导电填充材料相同的金属规格。

著录项

  • 公开/公告号DE102020120786A1

    专利类型

  • 公开/公告日2021-03-25

    原文格式PDF

  • 申请/专利权人 INTEL CORPORATION;

    申请/专利号DE202010120786

  • 申请日2020-08-06

  • 分类号H01L23/532;H01L29/417;H01L29/43;H01L29/78;

  • 国家 DE

  • 入库时间 2022-08-24 17:55:15

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