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DEFAULT ARC FOR COMPRESSION OF DETERMINISTIC FINITE AUTOMATA (DFA) DATA FLOW GRAPHS WITHIN A DATA FLOW GRAPH-DRIVEN ANALYTICS PLATFORM HAVING ANALYTICS HARDWARE ACCELERATORS
DEFAULT ARC FOR COMPRESSION OF DETERMINISTIC FINITE AUTOMATA (DFA) DATA FLOW GRAPHS WITHIN A DATA FLOW GRAPH-DRIVEN ANALYTICS PLATFORM HAVING ANALYTICS HARDWARE ACCELERATORS
An integrated circuit having a hardware-based regular expression (RegEx) engine configured to perform an analytical operation on a stream of data units. The RegEx engine receives a regular expression operation expressed as a finite automata (FA) graph having a plurality of nodes connected by directional arcs, each arc representing transitions between nodes of the FA graph based on criteria specified for the respective arc, the plurality of nodes including nodes, including a skip node, representing states in the regular expression operation. Beginning at a root node in the plurality of nodes, the RegEx engine steps through one or more nodes of the FA graph until arriving at a skip node and then skips N data units before transitioning on the default arc to another node in the graph.
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