首页> 外国专利> GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING STRAINED SOURCE OR DRAIN STRUCTURES ON GATE DIELECTRIC LAYER

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING STRAINED SOURCE OR DRAIN STRUCTURES ON GATE DIELECTRIC LAYER

机译：门 - 全围绕栅极介电层的应变源或漏极结构的全面集成电路结构

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摘要

Gate-all-around integrated circuit structures having strained source or drain structures on a gate dielectric layer, and methods of fabricating gate-all-around integrated circuit structures having strained source or drain structures on a gate dielectric layer, are described. For example, an integrated circuit structure includes an insulator layer above a substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator layer. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and on the insulator layer. A gate stack is surrounding a channel region of the vertical arrangement of horizontal semiconductor nanowires. The gate stack includes a high-k dielectric layer continuous with and having a same composition as the insulator layer.

机译：描述于栅极介电层上具有应变源或漏极结构的栅极 - 全部集成电路结构，以及制造具有在栅极介电层上具有应变源或漏极结构的栅极 - 全部集成电路结构的方法。例如，集成电路结构包括基板上方的绝缘层。水平半导体纳米线的垂直布置在绝缘体层上。一对外延源或漏极结构处于水平半导体纳米线的垂直布置和绝缘体层的第一和第二端。栅极堆叠围绕水平半导体纳米线的垂直布置的沟道区域。栅极堆叠包括高k介电层，与绝缘体层一起连续并具有与绝缘体层相同的组成。

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公开/公告号EP3930004A1

专利类型
公开/公告日2021-12-29

原文格式PDF
申请/专利权人 INTEL CORPORATION;
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申请/专利号EP20200214380
发明设计人 KAVALIEROS JACK T.;MURTHY ANAND S.;RACHMADY WILLY;AGRAWAL ASHISH;CHOUKSEY SIDDHARTH;KEECH RYAN;GANGULY KOUSTAV;
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申请日2020-12-15
分类号H01L29/775;H01L21/336;H01L29/06;H01L29/10;H01L29/08;H01L29/423;B82Y10;H01L27/092;H01L29/78;
国家 EP
入库时间 2022-08-24 23:05:33

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