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On the Reuse of RTL IPs for SysML Model Generation

机译：关于在SysML模型生成中重用RTL IP

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摘要

Model-based design is getting more and more consensus in the today embedded system design flows. In this context, SysML is becoming the de-facto reference modeling language as it allows designers to model a whole system, both HW and SW, at high levels of abstraction. The SysML description can be defined with different levels of detail, each one suitable to the design and functional verification requirements. In this paper, we propose a methodology for abstracting existing RTL IPs into SysML components. During the abstraction flow, it is possible to set the level of detail to be maintained in SysML, such as, hierarchical structure and data types of the IPs. However, the generated SysML models are complete of both structural and behavioral descriptions and, thus, they can be synthesized into C++, SystemC, or Java executable code for simulation by any commercial tool. As a consequence, the methodology relieves designers from the modeling time and error risks especially for those design and functional verification phases in which the SysML model of the HW architecture is particularly structured and detailed.
机译：在当今的嵌入式系统设计流程中，基于模型的设计越来越获得共识。在这种情况下，SysML成为事实上的参考建模语言，因为它允许设计人员以高度抽象的水平为整个系统（硬件和软件）建模。 SysML描述可以用不同的详细级别定义，每种级别都适合设计和功能验证要求。在本文中，我们提出了一种将现有RTL IP抽象为SysML组件的方法。在抽象流程中，可以设置要在SysML中维护的详细程度，例如IP的层次结构和数据类型。但是，生成的SysML模型包含结构和行为方面的描述，因此可以将其合成为C ++，SystemC或Java可执行代码，以通过任何商业工具进行仿真。结果，该方法使设计人员免于建模时间和错误风险，特别是对于那些在硬件结构的SysML模型特别结构化和详细化的设计和功能验证阶段。

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