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On the Reuse of RTL IPs for SysML Model Generation

机译：关于SYSML模型生成的RTL IP的重用

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Model-based design is getting more and more consensus in the today embedded system design flows. In this context, SysML is becoming the de-facto reference modeling language as it allows designers to model a whole system, both HW and SW, at high levels of abstraction. The SysML description can be defined with different levels of detail, each one suitable to the design and functional verification requirements. In this paper, we propose a methodology for abstracting existing RTL IPs into SysML components. During the abstraction flow, it is possible to set the level of detail to be maintained in SysML, such as, hierarchical structure and data types of the IPs. However, the generated SysML models are complete of both structural and behavioral descriptions and, thus, they can be synthesized into C++, SystemC, or Java executable code for simulation by any commercial tool. As a consequence, the methodology relieves designers from the modeling time and error risks especially for those design and functional verification phases in which the SysML model of the HW architecture is particularly structured and detailed.
机译：基于模型的设计在今天的嵌入式系统设计流中获得了越来越多的共识。在此上下文中，Sysml正在成为De-Facto参考建模语言，因为它允许设计人员在高水平的抽象中建模整个系统，包括HW和SW。可以使用不同级别的详细信息来定义SYSML描述，每个细节都适合设计和功能验证要求。在本文中，我们提出了一种将现有RTL IPS抽象到SYSML组件的方法。在抽象流期间，可以将详细的细节级别设置为在SYSML中维护，例如IP的层次结构和数据类型。但是，生成的SYSML模型是完整的结构和行为描述，因此，它们可以由任何商业工具进行模拟的C ++，Systemc或Java可执行代码。因此，该方法可从建模时间和错误风险中减轻设计者，特别是对于那些设计和功能验证阶段，其中HW架构的SYSML模型特别是结构和详细。

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