Efficient Architecture for Integral Image Computation on Heterogeneous FPGAs

机译：异构FPGA上集成图像计算的高效架构

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摘要

Integral image (IIM) is an intermediate image representation, employed in several computer vision algorithms. Although only simple arithmetic operations are required to compute an IIM, the total number of additions increases quadratically with the input image size. For this reason, the design of hardware architectures able to accelerate the IIM computation receives a great deal of attention. Unfortunately, existing solutions are not appropriate for the integration within high-performance embedded systems, which are currently realized within modern heterogeneous CPU-FPGA System on Chips (SoCs). In this paper, we present a novel hardware architecture for accelerating the IIM computation. The proposed design outperforms existing competitors by parallelizing operations along both rows and columns of the input image. Experiments, conducted on a Zynq-7000 XC7Z020 SoC, demonstrate that the novel accelerator achieves a speed per computation unit up to 124 times higher than prior works, saving more than 70Mbits of on-chip memory resources for 1920×1080 frame resolutions.

机译：积分图像（IIM）是一种中间图像表示形式，已在多种计算机视觉算法中使用。尽管只需要简单的算术运算就可以计算IIM，但是加法运算的总数随输入图像大小的平方增加。因此，能够加速IIM计算的硬件体系结构设计受到了广泛的关注。不幸的是，现有的解决方案不适用于高性能嵌入式系统中的集成，而当前在现代异构CPU-FPGA片上系统（SoC）中已经实现了这种集成。在本文中，我们提出了一种用于加速IIM计算的新颖硬件架构。拟议的设计通过沿输入图像的行和列并行化操作，胜过了现有竞争对手。在Zynq-7000 XC7Z020 SoC上进行的实验表明，该新型加速器的每个计算单元速度比以前的工作高出124倍，为1920×1080帧分辨率节省了70Mbit的片上存储器资源。

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《2019 15th Conference on Ph.D Research in Microelectronics and Electronics》|2019年|229-232|共4页
会议地点 Lausanne(CH)
作者
Fanny Spagnolo; Pasquale Corsonello; Stefania Perri;
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作者单位

Department of Informatics, Modeling, Electronics and System Engineering, University of Calabria, Rende, Italy;

Department of Informatics, Modeling, Electronics and System Engineering, University of Calabria, Rende, Italy;

Department of Mechanical, Energy and Management Engineering, University of Calabria, Rende, Italy;

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原文格式 PDF
正文语种 eng
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Hardware; Field programmable gate arrays; Parallel processing; Clocks; Embedded systems; Memory management;

机译：硬件;现场可编程门阵列;并行处理;时钟;嵌入式系统;内存管理;;

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1. Energy-Efficient Dataflow Computations on FPGAs using Application-Specific Coarse-Grain Architecture Synthesis [J] . Colin Yu Lin, Hayden Kwok-Hay So Computer architecture news . 2012,第5期

机译：使用专用粗粒度体系结构综合的FPGA上的节能数据流计算
2. A real-time FPGA architecture for 3D reconstruction from integral images [J] . D. Chaikalis, N.P. Sgouros, D. Maroulis Journal of visual communication & image representation . 2010,第1期

机译：用于从积分图像进行3D重建的实时FPGA架构
3. An efficient FPGA architecture for integer nth root computation [J] . Rangel-Valdez Nelson, Hugo Barron-Zambrano Jose, Torres-Huitzil Cesar, International journal of electronics . 2015,第10a12期

机译：高效的FPGA架构，可进行整数n次根运算
4. Efficient Architecture for Integral Image Computation on Heterogeneous FPGAs [C] . Fanny Spagnolo, Pasquale Corsonello, Stefania Perri Conference on Ph.D Research in Microelectronics and Electronics . 2019

机译：非均质FPGA上积分图像计算的高效架构
5. Efficient algorithm and architecture for implementation of multiplier circuits in modern FPGAs. [D] . Athow, Jacques Laurent. 2008

机译：在现代FPGA中实现乘法器电路的高效算法和架构。
6. Integral Images: Efficient Algorithms for Their Computation and Storage in Resource-Constrained Embedded Vision Systems [O] . Shoaib Ehsan, Adrian F. Clark, Naveed ur Rehman, 2015

机译：积分图像：在资源受限的嵌入式视觉系统中进行有效计算和存储的算法
7. A heterogeneous architecture for evaluating real-time one-dimensional computational fluid dynamics on FPGAs [O] . Isaac Liu, Edward A. Lee, Matthew Viele, 2012

机译：一种用于评估FPGA上实时一维计算流体动力学的异构体系结构
8. Efficient Numeric and Geometric Computations using Heterogeneous Shared Memory Architectures. [R] . Manocha, D. 2017

机译：使用异构共享存储器架构的高效数字和几何计算。

Efficient Architecture for Integral Image Computation on Heterogeneous FPGAs

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