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首页> 外文会议>18th Symposium on Microelectronics Technology and Devices; 16th Symposium on Integrated Circuits and System Design; Sep 8-11, 2003; Sao Paulo, Brazil >AN IMPROVED CURRENT MODEL FOR EDGELESS SOI MOSFETs
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AN IMPROVED CURRENT MODEL FOR EDGELESS SOI MOSFETs

机译：无边SOI MOSFET的改进电流模型

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摘要

The most common current model for an edgeless transistor is obtained by taking the rectangular device drain current expression and substituting the device width by an "equivalent" device width, usually given by the average between source and drain width of the channel. However, this model does not take into account some effects that take place near the corners of the device. This work presents for the first time a current model for thin-film, fully depleted SOI edgeless devices, using the asymmetric trapezoidal gate approach. Three-dimensional numerical simulation is used as a first reference for model validation. Some experimental results from different edgeless SOI devices, with width-length ratio varying in a wide range were carried out, as an additional validation approach. Both simulation and experimental results show that the proposed model presents an improved performance, and it is still simple to be applied.
机译：通过采用矩形器件漏极电流表达式并将器件宽度替换为“等效”器件宽度（通常由沟道的源极和漏极宽度之间的平均值给出），可获得无边缘晶体管的最常见电流模型。但是，该模型没有考虑在设备角落附近发生的某些影响。这项工作首次提出了使用不对称梯形栅极方法的薄膜，全耗尽SOI无边缘器件的当前模型。三维数值模拟被用作模型验证的第一参考。作为一种附加的验证方法，从宽边长比在宽范围内变化的不同无边SOI器件进行了一些实验结果。仿真和实验结果均表明，所提出的模型具有改进的性能，并且仍然易于应用。

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