Evaluation of 35nm MOSFET capacitance components in PSP compact model

机译：在PSP紧凑模型中评估35nm MOSFET电容组件

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In this paper the capacitance components of the PSP compact model which is selected as successor of BSIM4 by the Compact Modelling Council (CMC) are investigated and simulated in HSPICE for the state of the art 35nm MOSFET device. The simulations are compared with TCAD results in both transcapacitance components between the device terminals and time domain to show the impact of accuracy of compact model on real circuit simulations.

机译：在本文中，针对最新的35nm MOSFET器件，在HSPICE中研究并仿真了由紧凑型建模委员会（CMC）选择为BSIM4的PSP紧凑型模型的电容组件。将仿真与设备终端之间的跨电容分量和时域中的TCAD结果进行了比较，以显示紧凑模型的精度对实际电路仿真的影响。

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来源
《2010 18th Iranian Conference on Electrical Engineering》|2010年|p.368-371|共4页
会议地点 Isfahan(IR);Isfahan(IR)
作者
Dideban Daryoosh; Cheng Binjie; Moezi Negin; Wang Xingsheng; Asenov Asen;
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作者单位

Device Modelling Group, University of Glasgow, UK;

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原文格式 PDF
正文语种 eng
中图分类真空电子技术;
关键词
Compact Modelling; PSP; TCAD; Transcapacitance; nanoCMOS;

机译：紧凑建模; PSP; TCAD;跨电容; nanoCMOS;

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专利

1. Compact Charge And Capacitance Modeling Of Undoped Ultra-thin Body (utb) Soi Mosfets [J] . Oana Moldovan, Ferney A. Chaves, David Jimenez, Solid-State Electronics . 2008,第12期

机译：未掺杂的超薄体Mosfets的紧凑电荷和电容建模
2. Carrier-based compact modeling of charge and capacitance of long channel undoped symmetric double-gate MOSFETs [J] . Jin He, Wei Bian, Yu Chen, Semiconductor science and technology . 2008,第4期

机译：基于载波的长沟道非掺杂对称双栅MOSFET电荷和电容的紧凑模型
3. Compact Modeling of the Effects of Parasitic Internal Fringe Capacitance on the Threshold Voltage of High-k Gate-Dielectric Nanoscale SOI MOSFETs [J] . M. Jagadesh Kumar, Sumeet Kumar Gupta, Vivek Venkataraman IEEE Transactions on Electron Devices . 2006,第4期

机译：寄生内部边缘电容对高k栅介电纳米级SOI MOSFET阈值电压影响的紧凑模型
4. Evaluation of 35nm MOSFET Capacitance Components in PSP Compact Model [C] . Daryoosh Dideban, Binjie Cheng, Negin Moezi, Iranian Conference on Electrical Engineering . 2010

机译：PSP紧凑型模型中35nm MOSFET电容分量的评估
5. Compact modeling of Silicon Carbide (SIC) Vertical Junction Field Effect Transistor (VJFET) in PSpice using Angelov model and PSpice simulation of analog circuit building blocks using SIC VJFET model. [D] . Purohit, Siddharth. 2006

机译：使用Angelov模型在PSpice中对碳化硅（SIC）垂直结场效应晶体管（VJFET）进行紧凑建模，并使用SIC VJFET模型对PSpice模拟电路构建模块进行仿真。
6. A quasi-ballistic drain current charge and capacitance model with positional carrier scattering dependency valid for symmetric DG MOSFETs in nanoscale regime [O] . Vyas R. Murnal, C. Vijaya 2019

机译：具有位置载流子散射相关性的准弹道漏电流电荷和电容模型对纳米级对称DG MOSFET有效
7. Compact Modeling of Parasitic Internal Fringe Capacitance Effects on the Threshold Voltage of High-K Gate Dielectric Nanoscale SOI MOSFETs [O] . Kumar, M. Jagadesh, Gupta, Sumeet Kumar, Venkataraman, Vivek 2010

机译：寄生内部边缘电容效应的紧凑建模高K栅介质纳米级sOI mOsFET的阈值电压
8. Compact Modeling of the Dynamic Behaviour of MOSFETS [R] . Smedes, T. 1991

机译：mOsFETs动态特性的紧凑建模

Evaluation of 35nm MOSFET capacitance components in PSP compact model

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