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首页> 外文会议>2011 IEEE Region 10 Conference: Trends and development in converging technology towards 2020 >Simple hardware verification platform using SystemVerilog
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Simple hardware verification platform using SystemVerilog

机译：使用SystemVerilog的简单硬件验证平台

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摘要

A simplified hardware verification platform based on layered approach is implemented using SystemVerilog. SystemVerilog unifies several proven hardware design and verification languages in the form of extensions to Verilog HDL. The importance of a verification platform based on OOP technique is increasing for high-level functional verification. The proposed platform consists of components such as generator, driver, monitor and checker which are connected by channels. The structure and test procedure based on Teal/Truss are changed to be as simple as possible for those who are not familiar with OOP to understand and use the platform easily.
机译：使用SystemVerilog实现了基于分层方法的简化硬件验证平台。 SystemVerilog以Verilog HDL的扩展形式统一了几种成熟的硬件设计和验证语言。对于高级功能验证而言，基于OOP技术的验证平台的重要性日益提高。所建议的平台包括通过通道连接的组件，例如发电机，驱动器，监视器和检查器。基于Teal / Truss的结构和测试过程已更改为对那些不熟悉OOP的人来说，尽可能简单地理解并轻松使用该平台。

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