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首页> 外文会议>2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip >Simulation framework for cycle-accurate RTL modeling of partial run-time reconfiguration in VHDL
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Simulation framework for cycle-accurate RTL modeling of partial run-time reconfiguration in VHDL

机译：VHDL中部分运行时重新配置的精确周期RTL建模的仿真框架

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摘要

Partial run-time reconfiguration has brought forward a new dimension and many new possibilities when designing systems. However, it also leads to many new challenges that need to be addressed for partial run-time reconfiguration to be successful. One of the most significant challenges is how to perform functional verification of systems using partial run-time reconfiguration. In this paper, we propose a simulation framework for functional modeling and verification of partial run-time reconfiguration at the Register Transfer Level (RTL) using VHDL. The proposed simulation framework provides cycle-accurate modeling of the reconfiguration process using the real bitstream file, and supports both island-based and slot-based reconfigurable design styles. For slot-based design styles, the simulation framework supports modules that either occupies one slot or multiple slots, as well as module relocation.
机译：在设计系统时，部分运行时重新配置带来了新的维度和许多新的可能性。但是，这也带来了许多新挑战，要使部分运行时重新配置成功，就需要解决这些挑战。最重大的挑战之一是如何使用部分运行时重新配置对系统执行功能验证。在本文中，我们为使用VHDL在寄存器传输级别（RTL）进行功能建模和部分运行时重新配置验证提供了一个仿真框架。拟议的仿真框架使用真实的比特流文件提供了重新配置过程的精确周期建模，并支持基于岛和基于插槽的可重新配置设计样式。对于基于插槽的设计样式，仿真框架支持占用一个插槽或多个插槽的模块，以及模块重定位。

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