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首页> 外文会议>2013 International Workshop on Microwave and Millimeter Wave Circuits and System Technology >A generalized low power and lower jitter charge pump PLL
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A generalized low power and lower jitter charge pump PLL

机译：通用的低功耗和低抖动电荷泵PLL

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In this paper, design a fast locking time and low jitter PLL based on Self-Biased technology. The PLL designs achieve process technology independent, broad frequency range and low input tracking jitter. The loop bandwidth will track operating frequency, therefore, sets no constraint on the operating frequency range. Self-biasing avoids the necessity for external biasing, by generating all of the internal bias voltages and currents from each other so that the bias levels are completely determined by the operating conditions. The PLL is implemented in SMIC 0.13µm MS/RF 1P8M CMOS technology. The design is simulated by a software called Cadance spectre, and the layout is shown. Simulation results show that this circuit can achieve a very wide tuning range is 500MHz to 2 GHz and the phase noise is −91.08dBc/Hz@1MHz, the jitter RMS value is 4.9ps in central frequency at 1.25GHz and the die area of the PLL is 250um × 420um.The power dissipation of the PLL core is only 10mW at a 1.2V supply.
机译：本文设计了一种基于自偏置技术的快速锁定时间和低抖动PLL。 PLL设计实现了独立于工艺技术，宽频率范围和低输入跟踪抖动。环路带宽将跟踪工作频率，因此，对工作频率范围没有任何限制。自偏置通过彼此产生所有内部偏置电压和电流来避免外部偏置，因此偏置水平完全由工作条件决定。 PLL采用SMIC 0.13µm MS / RF 1P8M CMOS技术实现。使用称为Cadance Spectre的软件对设计进行仿真，并显示布局。仿真结果表明，该电路可以实现非常宽的调谐范围，范围为500MHz至2 GHz，相位噪声为−91.08dBc/Hz@1MHz，中心频率为1.25GHz时，抖动RMS值为4.9ps。 PLL为250um×420um.1.2V电源时，PLL内核的功耗仅为10mW。

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