From double to triple gate: Modeling junctionless nanowire transistors

机译：从双闸到三闸：建模无结纳米线晶体管

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摘要

This paper presents a continuous, physically and charge-based new model for triple gate junctionless nanowire transistors (3G JNT). The presented model was evolved from a previous one designed for double gate junctionless transistors (2G JNT). The capacitance coupling and the internal potential changing from 2G to 3G JNTs are considered. The model validation is performed through both numerical simulation and experimental measurements for long and short channel devices.

机译：本文提出了一种基于连续，基于物理和电荷的三栅极无结纳米线晶体管（3G JNT）新模型。提出的模型是从先前为双栅极无结晶体管（2G JNT）设计的模型演变而来的。考虑了电容耦合和内部电位从2G到3G JNT的变化。通过对长通道和短通道设备进行数值模拟和实验测量来进行模型验证。

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来源
《2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon》|2015年|5-8|共4页
会议地点 Bologna(IT)
作者
Cardoso Paz Bruna; Pavanello Marcelo Antonio; Casse Mikael; Barraud Sylvain; Reimbold Gilles; Faynot Olivier; Avila-Herrera Fernando; Cerdeira Antonio;
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作者单位

Dept. of Electr. Eng., Centro Univ. da FEI, São Bernardo do Campo, Brazil;

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会议组织
原文格式 PDF
正文语种 eng
中图分类
关键词
Junctionless; measurements; modeling; simulation; triple gate;

机译：无结；测量；建模；仿真；三重门;

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1. Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors [J] . Trevisoli Renan, Doria Rodrigo Trevisoli, Barraud Sylvain, Microelectronic Engineering . 2019,第Jula期

机译：在三栅极SOI无结纳米线晶体管中模拟与接口陷阱相关的低频噪声
2. Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors [J] . Trevisoli Renan, Doria Rodrigo Trevisoli, Barraud Sylvain, Microelectronic Engineering . 2019,第JULa期

机译：在三栅极SOI无结纳米线晶体管中模拟与接口陷阱相关的低频噪声
3. Errata to “Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors” [J] . Trevisoli Renan, Doria Rodrigo Trevisoli, de Souza Michelly, Electron Devices, IEEE Transactions on . 2016,第1期

机译：勘误表“三栅极无结纳米线晶体管的基于表面电势的漏极电流分析模型”
4. From double to triple gate: Modeling junctionless nanowire transistors [C] . Cardoso Paz Bruna, Pavanello Marcelo Antonio, Casse Mikael, Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon . 2015

机译：从DOUBL到Triple Gate：建模连接纳米线晶体管
5. Nanowire-based devices for electronic and optical applications: Solution-gated silicon nanowire field effect transistors and one-dimensional gold nanoparticle arrays [D] . Hu, Wenchong 2010

机译：用于电子和光学应用的基于纳米线的设备：溶液门控硅纳米线场效应晶体管和一维金纳米粒子阵列
6. Electrical property comparison and charge transmission in p-type double gate and single gate junctionless accumulation transistor fabricated by AFM nanolithography [O] . Arash Dehzangi, A Makarimi Abdullah, Farhad Larki, 2012

机译：AFM纳米光刻制造的p型双栅极和单栅极无结累积晶体管的电性能比较和电荷传输
7. A Two Dimensional Surface Potential Model for Triple Material Double Gate Junctionless Field Effect Transistor [O] . Kumar A., Chaudhry A., Kumar V., 2016

机译：三材料双栅无结场效应晶体管的二维表面势模型

From double to triple gate: Modeling junctionless nanowire transistors

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