Analysis of p-type Junctionless nanowire transistors with different crystallographic orientations

机译：具有不同晶体学取向的p型无结纳米线晶体管的分析

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This work presents an analysis of the influence of the crystal orientation on the performance of p-type Junctionless Nanowire Transistors. The main electrical parameters, such as threshold voltage, transconductance and subthreshold slope, were analyzed by means of experimental data, demonstrating that the substrate rotation can significantly worsen the electrical behavior of these devices.

机译：这项工作提出了晶体取向对p型无结纳米线晶体管性能的影响的分析。通过实验数据分析了主要电参数，例如阈值电压，跨导和亚阈值斜率，证明了基板旋转会大大恶化这些器件的电性能。

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来源
《2017 32nd Symposium on Microelectronics Technology and Devices》|2017年|1-4|共4页
会议地点 Fortaleza(BR)
作者
Renan Trevisoli; Rodrigo T. Doria; Michelly de Souza; Marcelo A. Pavanello;
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作者单位

Centro Universitário FEI, Department of Electrical Engineering - Sao Bernardo do Campo, Brazil;

Centro Universitário FEI, Department of Electrical Engineering - Sao Bernardo do Campo, Brazil;

Centro Universitário FEI, Department of Electrical Engineering - Sao Bernardo do Campo, Brazil;

Centro Universitário FEI, Department of Electrical Engineering - Sao Bernardo do Campo, Brazil;

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会议组织
原文格式 PDF
正文语种 eng
中图分类
关键词
Logic gates; Standards; Transconductance; Threshold voltage; Performance evaluation;

机译：逻辑门;标准;跨导;阈值电压;性能评估;;

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1. Characteristic of p-Type Junctionless Gate-All-Around Nanowire Transistor and Sensitivity Analysis [J] . Han M.-H., Chang C.-Y., Jhan Y.-R., Electron Device Letters, IEEE . 2013,第2期

机译：p型无结全栅纳米线晶体管的特性及灵敏度分析
2. Variability characteristics and corner effects of gate-all-around (GAA) p-type poly-Si junctionless nanowire/nanosheet transistors [J] . Ahn Min-Ju, Saraya Takuya, Kobayashi Masaharu, Japanese journal of applied physics . 2021,第SB期

机译：门 - 全周（GAA）P型多Si结纳米线/纳米片晶体管的可变性特性和角效应
3. Superior subthreshold characteristics of gate-all-around p-type junctionless poly-Si nanowire transistor with ideal subthreshold slope [J] . Ahn Min-Ju, Saraya Takuya, Kobayashi Masaharu, Japanese journal of applied physics . 2020,第7期

机译：具有理想亚阈值斜坡的门 - 全面P型连接多Si纳米线晶体管的卓越的亚阈值特性
4. Analysis of p-type Junctionless nanowire transistors with different crystallographic orientations [C] . Renan Trevisoli, Rodrigo T. Doria, Michelly de Souza, Symposium on Microelectronics Technology and Devices . 2017

机译：不同晶体取向的p型结纳米线晶体管分析
5. Modeling, Design, and Analysis of III-V Nanowire Transistors and Tunneling Transistors [D] . Khayer, Mohammad Abul 2011

机译：III-V纳米线晶体管和隧穿晶体管的建模，设计和分析
6. Electrical property comparison and charge transmission in p-type double gate and single gate junctionless accumulation transistor fabricated by AFM nanolithography [O] . Arash Dehzangi, A Makarimi Abdullah, Farhad Larki, 2012

机译：AFM纳米光刻制造的p型双栅极和单栅极无结累积晶体管的电性能比较和电荷传输
7. Electrical transfer, carrier concentration and surface charge analysis of a single-gated cylindrical channel junctionless p-type nanowire field-effect transistor for sensor applications [O] . Umapathi Krishnamoorthy, Sathish Kumar Shanmugam 2021

机译：用于传感器应用的单门控圆柱通道连接P型纳米线效应晶体管的电气传递，载流子浓度和表面电荷分析

Analysis of p-type Junctionless nanowire transistors with different crystallographic orientations

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